As faster operation of computers has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One widely incorporated feature directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. Thus, during a given time increment, a first stage of a fourth (in order of execution) instruction may be undertaken while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all undertaken simultaneously. This procedure dramatically increases the speed of operation of a computer system.
The execution of certain instructions, such as multi-word instructions, requires holding the pipe in one stage for a plurality of clock phases. An example of such instructions in the data processing system forming the environment of the exemplary embodiment is the family of Extended Instruction Set (EIS) instructions. The EIS instructions are functionally centered around sequences of basic operations functions, and a number of intra-execution sequence and/or control decisions must be made based on the characters being processed. The main instruction controller is too far removed from the data upon which the decisions must be made to efficiently control the sequence of the basic operations necessary to execute these instructions. The result, in the absence of the application of the present invention, is very slow EIS instruction execution and a requirement for much more micro-code than will readily fit within the address and execution integrated circuit chip.
It may be noted that a directly corresponding problem exists in processors which do not employ a pipeline, but do include in their repertoires instructions which require unusually extensive data manipulation extending over several clock cycles. The present invention also finds application in such processors.